Read-only memories (ROMs) are generally used for storing permanent programs or data for microprocessor systems. For example, the so-called BIOS of computer systems can be stored on such a ROM. Such ROMs are already programmed, i.e. set with data, during the production process. There are ROMs for which the programming takes place by interruption of diffusion layers (so-called “diffusion programmable ROM”). For another type of ROM, the programming takes place by selective setting of vertical metal connections (so-called “via programmable ROM” or “metal programmable ROM”, generally “mask programmable ROM”) between metal or other conducting layers. The latter type of ROMs has the advantage that the programming only occurs at a relatively late stage in the production process, so that there can be a common manufacturing process until this point for various ROMs to be programmed. Furthermore, the correction of faults in the planned programming is possible up to this production step relatively at the end of the process. Both types of ROMs are described for example in the U.S. patent application No. 2002/0039305 A1.
Another type of “via programmable ROM” is presented in FIGS. 3 and 4, FIG. 3 schematically showing a layout of such a ROM and FIG. 4 showing a schematic circuit diagram of the ROM from FIG. 3.
The ROM presented in FIG. 3 comprises—in a manner widely used for memory modules generally—a matrix of memory cells, in this case two columns each of four memory cells. As indicated in FIG. 3, either a value “0” or a value “1” can be stored in each memory cell. Naturally, memory modules in practice contain considerably more memory cells than the eight memory cells shown in FIG. 3, which are then correspondingly arranged in considerably more columns and rows, and optionally also over one another in several layers.
The functioning of the ROM will first be explained with reference to the schematic circuit diagram of FIG. 4, before returning to the implementation of the layout.
The individual memory cells are each implemented in the presented ROM by a transistor T1, T2, . . . , T8. Four word or address lines WL0, WL1, WL2 and WL3, each connected to the gates of two of the transistors T1–T8, are used for addressing the memory cells. For example, the address line WL0 is connected to the gates of the transistor T1 and the transistor T5.
The memory cells are then read over bit lines BL0 and BL1. For example, the address line WL0 and bit line BL0 are used for controlling and reading the transistor T1, while for controlling and reading the transistor T7 the address line WL2 and bit line BL1 are used. A specific combination of address and bit line thus uniquely determines the memory cell to be read.
The transistors T1–T8 are balanced in the layout, meaning that source and drain contact are in principle identical and thus interchangeable. The source and drain contacts of the transistors arranged in a column (T1–T4 or T5–T8) are connected to one another as shown. Connection lines 2A, 2B, . . . , 2J are further provided, which are provided between the individual transistors and at the beginning and end of each column, and connected as shown. The totality of the connection lines 2A–2J is denoted in the following simply with the reference label 2. Each of the connection lines 2 is connected either to one of the bit lines BL0, BL1 or to a potential line 6. In the example shown, the potential line 6 is for example a virtual negative potential line (“virtual VSS”). Virtual in this context means that the potential line 6 is on a positive supply voltage in an “idle state”. If a memory cell in the corresponding column of the ROM is read, the corresponding potential line 6 is connected to negative supply voltage.
Furthermore, in a normal state of the circuit, the bit lines BL0 and BL1 for example are on the negative supply voltage. To read a memory cell, the bit line of the corresponding circuit is connected to the positive supply voltage, which represents the logical state “1”.
If the memory cell formed by the transistor T1 is now to be read, for example, the left potential line 6 in FIG. 4 is initially connected to the negative supply voltage and the bit line BL0 to the positive supply voltage. The address line WL0 is then switched from negative to positive supply voltage, so that the transistor T1 becomes conductive. A current can thus flow over the connection line 2A, the transistor T1 and the connection line 2B from the left potential line 6 to the bit line BL0. The bit line BL0 is thereby drawn to negative supply voltage, which corresponds to a logical “0” and thus to the contents of the memory cell formed by the transistor T1.
In contrast, if the transistor T6, which has a stored logical “1”, is read, no current can flow from the right potential line 6 to the bit line BL1, as neither the connection line 2G nor the connection line 2H is connected to the bit line BL1. A current over the transistor T5 which in this case is realized as field-effect transistors for example can likewise not flow, as the address line WL0 remains on negative supply voltage; only the address line WL1 is switched from negative to positive supply voltage, in order to read the transistor T6.
Naturally, it is possible in principle to swap the polarity of the transistors T1–T8, and simultaneously change the potential used for the reading on the address lines WL0–WL3. In the same way it is feasible, in principle, before the reading to connect the corresponding bit line to negative supply voltage and the corresponding potential line 6 to positive supply voltage, which would mean the reverse memory state in each case for the respective transistors.
In the layout of FIG. 3 corresponding to the circuit diagram of FIG. 4, the lowest layer is formed by two diffusion layers 1A, 1B, in other words by doped semiconductor layers, preferably silicon, to form a semiconductor part of the transistors T1–T8 from FIG. 4. Above this run the address lines WL0–WL3, which are formed for example from polysilicon, preferably from high-doped polycrystalline silicon, and serve as a gate for the transistors T1–T8. For example, when an address line is on negative supply voltage VSS, the section of the diffusion layer 1A or 1B underlying the respective address line is nonconductive. If the corresponding address line WL0–WL3 is on positive supply voltage VDD, the section of the diffusion layer 1A or 1B underlying the respective address line becomes conductive.
A first metal layer comprises the connection lines 2 in the form of metal sections. These are connected with electrical conductivity by metal contacts 3A–3J to the diffusion layer, and form source and drain contacts of the transistors T1–T8. As already mentioned, these transistors are balanced in the layout, meaning that there is no fixed source or drain contact. The source and drain contacts are also divided for the transistors in the FIG. 3 layout. Thus, the connection lines 2A and 2B represent source and drain contacts of the transistor T1, and the connection lines 2B and 2C are the source and drain contacts of the transistor T2. The connection line 2B is thus a contact of both the transistor T1 and the transistor T2.
A second metal layer contains the bit lines BL0 and BL1, and the potential lines 6. The first metal layer is separated from the second metal layer by a suitable insulation, for example of silicon dioxide.
Metal connections 7 (“vias”) connect the lines 2 at desired points to the potential line 6, metal connections 8 (“vias”) connect the bit lines BL0 and BL1 to the lines 2. The metal connections 7 and 8 are set such that the corresponding programming of the ROM is achieved. As can be seen especially for the right of the potential lines 6, the metal sections 2G–2J, which represent contacts of the transistors T6–T8 programmed to “1”, are connected to the potential line 6, so that these metal sections are on a defined potential.
Such a layout is also called “wide cell” architecture, since relatively short bit lines BL0 and BL1 are implemented here—by the use of common connection lines 2 for two transistors at a time, among other things—so that there is a relatively wide cell in the view of FIG. 3. This implementation is especially suitable for ROMs that are to be operated with low voltage. Layouts in which the bit lines are conversely longer than the address lines are called “tall cells”.
The ROM shown in FIG. 3 and 4 has the disadvantage that couplings can occur between individual memory cells or the bit lines, so that when a “1” is read, an adjacent programmed “0” can influence the read result. This coupling is due to parasitic capacitances, of the bit lines for example.